Increasingly with integrated circuits, a high density of transistors is being provided leading to relatively large circuits. The interconnects, as a result, become longer and more resistive. With shrinking feature sizes, the relative resistivity of the wires is increased. Furthermore, as integrated circuit design evolves, the voltages used are being reduced leading to an increase in the signal's delay. Increasingly, high speed clocks are used on integrated circuits with multi-clock islands for better system on chip (SoC) performances. A portion of the system power consumption comes from clock signals. Clock gating technique is a low power technique that reduces the switching activity of transistors and hence reduces the consumed power.
These trends lead to problems in signal delays, skewing and signal racing which can result in metastability. In the case of a gated clock, the clock may be glitchy which can adversely affect performance.